1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly a semiconductor memory device that can retain stored data without executing a refresh operation.
2. Description of the Background Art
A scheme of reducing power consumption in a random access memory during data writing is disclosed in Japanese Patent Laying-Open No. 2002-366419.
The conventional data processor disclosed in the aforementioned publication detects the number of “0”s and the number “1”s during data writing, and writes, when the number of “0”s is low, inverted data together with flag information indicative of whether data has been inverted or not. In a reading mode, the data is inverted in accordance with the flag information. Since the frequency of inverting data stored in the memory cell is reduced, power consumption in a data writing mode can be reduced.
The conventional data processor disclosed in the aforementioned publication includes a circuit comparing the number of “0”s and the number of “1”s using an adder. In the case where multi-bit data is input, the number of stages of logic circuits will be increased. This poses the problem that the delay time is increased and the circuit complexity becomes higher. The aforementioned publication corresponding to a data processor fails to teach a specific circuit configuration of the memory.
In the case where a memory block is formed of memory cells of a general single port SRAM (Static Random Access Memory) in the conventional data processor disclosed in the aforementioned publication, the potential level of one of bit lines forming a pair will always be altered in a reading operation. Thus, there was a problem that power is consumed by the charging/discharging operation of a bit line every time reading is conducted.
In a data processor such as the type disclosed in the aforementioned publication, data stored through one writing operation is often read-out subsequently many times. This means that the access frequency of the microprocessor in such a data processor to a memory cell is higher in a read out operation than in a write operation. It is therefore more effective to reduce the power consumption during a reading mode than in a writing mode in order to reduce the power consumption during memory access. However, the conventional data processor disclosed in the aforementioned publication is directed to reduce power consumption during a writing operation. Such a data processor is disadvantageous in that power consumption during a reading operation is not lowered.
Reflecting the microminiaturization of semiconductor integrated circuits, the SRAM mounting complexity on one chip has become higher. In accordance with the higher SRAM mounting complexity, a plurality of memory blocks will be mounted within one chip. As a result, not only the power consumption due to a reading or writing operation in a memory block that is accessed, i.e. in an operation state, but also power consumption caused by standby leakage current in a memory block that is not accessed, i.e. in a standby state, will become greater.
When the gate length of an MOS transistor becomes less than 1 μm in accordance with microminiaturization of semiconductor integrated circuits, the gate insulation film will also become as thin as approximately 10–20 Å. Accordingly, the gate tunnel leakage current that was negligible so far increases, resulting in further increase of the standby leakage current in a standby state. Therefore, lowering the standby leakage current in the SRAM has become an important element in reducing the power consumption of the entire chip. The conventional data processor disclosed in the aforementioned publication is directed to reducing power consumption in a writing operation, and is not directed to reducing the power consumption in a standby state.
In the case where a memory block is formed of memory cells of a general single port SRAM in a conventional data processor as disclosed in the aforementioned publication, the standby current flowing during a standby state is identical irrespective of whether the retaining data (write data) is 0 or 1. The effect of reducing the flow of standby leakage current during a standby state could not be achieved by just inverting the write data as in the conventional data processor disclosed in the aforementioned publication.